The past few years have seen a dramatic increase in the speed of data transmission capabilities among and between the various components of a computer system or between multiple computer systems connected together in a network configuration. Indeed, since the general acceptance of personal computer systems in the 1960's, data transmission speeds have grown with an almost power law dependence; about 1 MHz in the '60's, 10 MHz in the '70's, 100 MHz in the '80's and 1 GHz speeds being routinely achieved in the '90's.
The development of optical fibre for transmission of digital data streams has become a particular enabling technology for modern-day 1 GHz data transmission speeds and, in the computer industry, has given rise to a data transfer protocol and interface system termed Fibre-Channel. Fibre-Channel technology involves coupling various computer systems together with optical fibre or a fibre channel compatible electrically conductive (copper) cable and allows extremely rapid data transmission speeds between machines separated by relatively great distances.
However, because of the physical characteristics of Fibre-Channel-type cable, present day systems are only capable of serial-fashion data transmission (at least when only a single optical fibre or electrical cable is used to interconnect various computer systems). In contrast, computer systems are internally configured to almost universally handle data in parallel fashion on byte-multiple signal busses (8-bit, 16-bit or 32-bit buses), making it incumbent on any data transmission system to provide some means for converting a 1 GHz serial data stream into a byte or byte-multiple parallel data stream. Conversely, since the Fibre-Channel protocol contemplates two-way data transmission, computer systems that typically operate with parallel data structures must have some means for serializing a byte or byte-multiple data stream into a 1 GHz data signal suitable for serial transmission down an optical fibre or an electrically conductive (copper) cable.
Parallel data is typically synchronously serialized for high speed transmission, i.e., the sequence of 1's and 0's making up the resulting serial data stream occurs with reference to a synchronized, uniform, single-frequency serializer clock signal. Encoding and transmitting the clock signal, together with data, would necessarily require an inordinate amount of valuable serial bandwidth and reduce the overall data transmission speed of a Fibre-Channel system. Even though some small degree of self-clocking is inherent in the serial data stream, some method of evaluating the data stream must be used in order that a transceiver or serial-to-parallel data recovery system may determine how to appropriately frame the serial data stream into bytes.
In accordance with the Fibre-Channel physical and signaling interface specification, defined in ANSI X3.230-1994, information to be transmitted over a fibre wire or cable is encoded, 8 bits at a time, into a 10-bit Transmission Character which is subsequently serially transmitted by bit. Data provided over a typical computer system's parallel architecture is encoded and framed such that each data byte (8-bits from the point of view of the computer system) is formed into a Transmission Character in accordance with the Fibre-Channel 8B/10B transmission code. The resulting 8B/10B character is then transmitted as 10 sequential bits at a 1.06 GHz data rate in accordance with the interface specification. Likewise, an incoming 8B/10B encoded transmission character must be serially received at a 1.06 GHz data rate and converted (framed) into the corresponding 10-bit transmission character. The 10-bit transmission character is then further decoded into an 8-bit byte recognizable by conventional computer architectures.
Pertinent to the 8B/10B transmission coding scheme is the fact that the number of sequential 1's and 0's in the resultant serial data stream is arbitrarily limited. In accordance with the Fibre-Channel physical and signaling interface specification, there may be no more than five sequential 1's and 0's in the serial data stream. It is important to realize that this limitation is applicable to the serial data stream as a whole and not to just a transmission character. A first transmission character comprising 1110001111 and a second transmission character comprising 1111001111 would violate the 8B/10B code limitation.
The reason for this limitation becomes evident when it is realized that the serial binary data stream is commonly transmitted in a "nonreturn-to-zero" (NRZ) format as illustrated in the exemplary waveform diagram of FIG. 1. As illustrated in the diagram, NRZ data is distinguished from "return-to-zero" (RZ) data in which the signal returns to a zero value between consecutive bits. In the NRZ case, each bit is defined by a "bit period", indicated in FIG. 1 as P.sub.b, and is statistically independent of any of the other bits. Fibre-Channel serial data is transmitted in an NRZ format because, for a given bit rate, NRZ data defines fewer transitions than RZ data making NRZ data preferable for transmission where channel or circuit bandwidth is costly. However, NRZ data comprises a particular attribute that makes the task of clock recovery difficult. Because of the relative absence of transition boundaries, NRZ data may exhibit long sequences of consecutive 1's or 0's, undifferentiated by a bit period marker, thus requiring a clock recovery circuit to "remember" the bit rate during such a sequential period. This means that in the absence of data transitions, the clock recovery circuit should not only continue to produce the clock but also incur negligible drift of the clock frequency. In order to minimize clock recovery circuit drift, the Fibre-Channel serial data stream is arbitrarily limited to five sequential bit periods comprising 1's and five sequential bit periods comprising 0's.
The most common clock recovery circuit is a phase-lock loop, which generates or regenerates asynchronous timing reference signal from a serial data stream and provides a timing reference to a data synchronizer or deserializer in order to mark in time the anticipated occurrence of a serial data bit. In effect, a phase-lock loop generates a synchronous stream of successive timing references, each timing reference representing, for example, a bit period T.sub.b with which a data bit may be associated. The phase-lock loop clock recovery circuit, accordingly, is an essential component in modern day GHz transceiver systems.
The frequency of clock signals recovered by, for example, a receiver phase-lock loop, is subject to a number of variations introduced by the electronic components of such systems. Typically, the electronic components in the data path introduce some elements of phase and frequency noise which are random in nature, and, more particularly, have dramatically varying bandwidth characteristics depending on the geometric and electronic variations in modern semiconductor manufacturing process parameters. Phase-lock loops such as comprises a 1.06 GHz to 106 MHz transceiver, must take these variations into account when attempting to deal with a 1.06 GHz serial data stream. Implementations of a 1.06 GHz to 106 MHz transceiver, including suitable phase-lock loop circuitry are described in co-pending U.S. Pat. applications Ser. Nos. 08/920,524, 08/924,009 and 08/924,028, all filed on Aug. 29, 1997 and commonly owned by the Assignee of the present invention, the entire disclosures of which are expressly incorporated herein by reference.
A particular feature of phase-lock loop system used in conjunction with a GHz serial data receiver is that such phase-lock loop systems may lose frequency or velocity lock in the event that the semiconductor manufacturing process used to implement the transceiver circuit causes the electronic characteristics of the PLL to inordinately drift such that the system exhibits a frequency deviation greater than the "lock range". The lock range is necessarily dependent on the bandwidth of the phase lock loop system but is commonly expressed as either a percentage of the mean frequency or some fixed value about the mean frequency. Since the operational frequency of a PLL corresponds to the VCO control voltage, in a fashion well understood by those having skill in the art, and since the VCO control voltage is, in turn, informed by the various semiconductor manufacturing process tolerances, it is easy to understand how semiconductor manufacturing tolerance drift is able to skew the operational frequency range of a phase-lock loop (PLL).
In order to determine whether a particular transceiver is functional with regard to operation at speed (1.06 GHz), it is necessary to exercise the transceiver circuit under operating conditions. Such an exercise is typically performed on a purpose-built semiconductor test apparatus which toggles the inputs of an integrated circuit in accordance with a pre-determined pattern and examines the pattern developed by the circuit output for conformance to a particular expected data pattern, or output mask. If the circuit's output pattern matches the expected data or mask pattern, the circuit is deemed to have "passed" meaning it is operational within its design performance parameters.
However, integrated circuit architectures are continually pushing the speed envelope, such that their inherent speed capabilities are almost always beyond the testing speed capabilities of integrated circuit testing apparatus. In the Fibre-Channel case, integrated circuit test apparatus are incapable of operationally exercising a 1.06 GHz integrated circuit at its operational data rate. Moreover, the large majority of integrated circuit test apparatus are incapable of exercising the 10-bit character bus at the required 106 MHz rate. Thus, some means must be implemented in the high-speed circuit itself to provide a measure of self-test capability such that the performance of the circuit may be evaluated at its operational 1.06 GHZ speed.
Previous high-speed integrated circuit designs have incorporated some means of internally generating test patterns useful for a built in self test (BIST) function, but prior-art integrated circuit data paths have typically been 8-bits wide and comprised no restriction to the number of sequential 1's or 0's generated by the pattern generator.
Pertinent prior art-type pattern generators suitably comprised an 8-bit linear feedback shift register (LFSR) which was able to pseudo-randomly generate a set of 255 patterns (out of a total of 256) at a data rate determined by a clock signal derived within the high-speed integrated circuit.
A typical prior art-type built in self test pattern generator using a linear feedback shift register is depicted in semi-schematic block diagram form in FIG. 2. In FIG. 2, the linear feedback shift register (LFSR) is implemented as eight sequential D-flip flops, each having a D input, a Q output, a clock (CLK) input and a set (SET) input. All of the clock inputs are tied to a clock signal CLK which is defined by the integrated circuit at issue and has a frequency equal to the operational speed of the chip. Each of the Q outputs of each of the D-flip flops are taken off to define an 8-bit wide bus with the righthand most Q output representing the least significant bit (LSB) and the left hand most Q output representing the most significant bit (MSB). The Q output of the LSB flip flop is directed to the input of the next-most significant bit D flip flop. Its Q output is, in turn, directed to the next-most significant flip flop, and so on down the string to the MSB flip flop. The output of the MSB flip flop is fed-back to the D input of the LSB flip flop through a 4-input exclusive OR (EXOR) gate. The other three inputs of the EXOR gate are taken from the Q outputs of the LSB flip flop, the next-most significant flip flop and the most significant-but-one flip flop.
The pattern result of such a configuration is depicted in the BIST pattern table of FIG. 3. At CLK time =0 (initialization) all of the D-flip flops are initialized to output 1's by strobing the SET inputs. As CLK toggles, the LFSR begins operation to generate the patterns depicted in the table of FIG. 3.
While able to shift data at high-speed rates, the LFSR of the prior art is unable to generate the unique patterns required for conformance to the Fibre-Channel 8B/10B transmission code. While the Fibre-Channel 8B/10B transmission code supports all 256 8-bit combinations, these combinations are expressed in 10-bit Transmission Characters. The Transmission Characters, themselves, are characterized by particular bit structure implementations such that, even for sequential Transmission Characters, no more than five sequential 1's and 0's may appear in the resulting serial data stream.
Accordingly, there is a demonstrated need for a built in self test system which operates in accordance with the frequency characteristics of a particular integrated circuit and is able to generate at least 255 out of 256 patterns representing valid transmission characters in accordance with 8B/10B encoding. Such a built in self test feature should be able to be easily implemented in a Fibre-Channel integrated circuit transceiver operating in accordance with a 1.06 GHz clock.